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12-19-2014, 09:10 AM
Aldec Active-HDL 10.1 (64bit) (December 19, 2014)
http://s16.postimg.org/65mcrbzyd/image.jpg
Aldec Active-HDL 10.1 (64bit) | 478.7 mb
Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL 10.1. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs.
Active-HDL is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language solution interfaces with nearly one hundred twenty (120) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. Active-HDL 10.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera, Lattice, Microsemi (Actel), Quicklogic and Xilinx.
More info: https://www.aldec.com/en/fpga_simulation/active-hdl
About Aldec
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.
DOWNLOAD LINKS:
http://rapidgator.net/file/5abae177eb8acaa08c36c2c440b79eae/dAcH10164b.rar.html
http://uploaded.net/file/b4sd3tjk/dAcH10164b.rar
http://www.uploadable.ch/file/XcbmaGkdpJJX/dAcH10164b.rar
http://s16.postimg.org/65mcrbzyd/image.jpg
Aldec Active-HDL 10.1 (64bit) | 478.7 mb
Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL 10.1. Popular with designers for more than 15 years for FPGA design entry and simulation due to its award-winning and intuitive GUI and high performance simulator, Active-HDL now offers support for 64-bit simulation to meet the growing demand of simulation of larger designs.
Active-HDL is an HDL-based FPGA Design and Simulation solution that supports the newest FPGA devices available from all leading FPGA vendors. The high-performance, mixed-language solution interfaces with nearly one hundred twenty (120) third party vendor tools and provides FPGA designers a single platform that can be used independently of the targeted FPGA design flow. Active-HDL 10.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera, Lattice, Microsemi (Actel), Quicklogic and Xilinx.
More info: https://www.aldec.com/en/fpga_simulation/active-hdl
About Aldec
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.
DOWNLOAD LINKS:
http://rapidgator.net/file/5abae177eb8acaa08c36c2c440b79eae/dAcH10164b.rar.html
http://uploaded.net/file/b4sd3tjk/dAcH10164b.rar
http://www.uploadable.ch/file/XcbmaGkdpJJX/dAcH10164b.rar