Network on Chip: Architecture, Optimization, and Design Explorations
ITexLi | 2022 | ISBN: 1839681586 9781839681585 1839681489 9781839681486 1839681594 9781839681592 | 90 pages | PDF | 8 MB
This book gives a detailed analysis of various on-chip communication architectures and covers different areas of network-on-chip (NoC)s such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. It discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.
Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system.
Contents
1. Direct and External Hybrid Modulation Approaches for Access Networks
2. MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip
3. Network-on-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction
4. A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour
5. Digital Control of Active Network Microstructures on Silicon Wafers
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